Actel Designer v8.0 英文正式版(FPGA器件開發軟體)
破解說明:
破解檔放置於crack夾內,請將破解檔複製於主程式的安裝目錄內既可破解
內容說明:
ACTEL Designer 是專業的FPGA器件開發軟體，是一個能使FPGA的系統性能提高15％的佈
局工具。Designer 是Actel的王牌設計實現工具套件。使用你喜歡的前端工具完成設計
輸入和功能驗證後,導入網表就能完成物理實現: 約束管理, 佈局布線, 時序及功耗分析,
器件編程。Designer 軟體對所有的Actel的FPGA設器件提供易用的和靈活的解決方案。它
使設計者能即插即用地使用業內領先的EDA工具, 如來自Synplicity, Mentor Graphics,
Synopsys, Cadence,Magma Design Automation和其它在EDA領域頂尖廠商的軟體。
Designer的高級佈局布線算法可以滿足今天不斷增長的複雜設計和密度的需要。建立在
Designers工具內部的建築專業技術使用戶可以建立最佳的設計。ActelDesigner軟體界
面提供圖形化和腳本流，以便適應你的設計環境。圖形設備優化可以通過MultiView
Navigator (MVN)和定時介面來實現。這些介面提供給專業用戶最大的靈活性去驅動
Place-and-route工具，以快速完成定時關閉。
英文說明:
Designer is Actel's powerful physical implementation
software tool suite. After completing design entry and
functional verification using Libero IDE tools or your
favorite front-end design tools, simply import the resulting
netlist into Designer before completing the physical and
timing constraints and performing place-and-route, timing
analysis, power analysis, and program file generation.
Designer provides full power optimization and analysis tools
for Actel's low-power
flash FPGA families, including the
IGLOO/e 1.2 V devices?the lowest power FPGAs on the
market.
Actel's Designer software offers an easy-to-use design
implementation solution for all Actel FPGA devices. It gives
you the flexibility either use Libero IDE's integrated tools
or other EDA tools from partners such as Synplicity, Mentor
Graphics, Synopsys, Cadence, and many other top names in the
EDA field.
Designer Software Features:
* Seamlessly compatible with: o Actel Libero
Integrated Design Environment (IDE) o Industry's
most popular synthesis tools o Popular
third-party schematic entry tools o VHDL and
Verilog simulation libraries * Support for established
EDA standards such as Verilog/VHDL/EDIF/VITAL/SDF/SDC *
SmartGen "correct by construction" library of configurable
logic and memory cores * MultiView Navigator provides
physical constraint editing plus cross-probing and other
design viewing capabilities with the following tools:
o ChipPlanner ?device-level floorplanning tool
o PinEditor ?package pin assignment tool o I/O
Attribute Editor ?set characteristics of I/O pins
o NetlistViewer ?design schematic viewer *
Timing-driven place-and-route * SmartPower provides
comprehensive power analysis features to assist in low power
optimization * SmartTime static timing analysis and
constraints management *
flashLock design security
programming software * Silicon Explorer ?real-time
debugging software * Tcl ?commonly used scripting
language * Actel simulation libraries
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